Operations
This page tells you which Operations are currently implemented for each architecture.
- ❌ Means it is not implemented.
- ✅ Means it is implemented.
- ❓ Means 'not applicable'.
Needed for Basic Hooking Support
Architecture |
Supported |
Notes |
x64 |
✅ |
+-2GiB |
x86 |
✅ |
+-2GiB |
ARM64 (+- 128MiB) |
✅ |
+-128MiB |
ARM64 (+- 4GiB) |
✅ |
Uses 3 instructions. Used if within range. |
Architecture |
Supported |
Notes |
x64 |
✅ |
Uses scratch register for efficiency. |
x86 |
✅ |
Uses scratch register for efficiency. |
ARM64 |
✅ |
Uses scratch register (required) |
Architecture |
Supported |
Notes |
x86 |
✅ |
|
x86 |
✅ |
|
ARM64 |
❌ |
Variant 0. |
ARM64 |
✅ |
Variant 1. Replaced with JumpAbsolute, for perf reasons. |
Needed for Wrapper Generation
Architecture |
Register to Register |
Vector to Vector |
x64 |
✅ |
✅ |
x86 |
✅ |
✅ |
ARM64 |
✅ |
✅ |
Architecture |
to Register |
to Vector |
x64 |
✅ |
✅ |
x86 |
✅ |
✅ |
ARM64 |
✅ |
✅ |
Architecture |
to Register |
to Vector |
x64 |
✅ |
✅ |
x86 |
✅ |
✅ |
ARM64* |
❌ |
❌ |
This is not needed for optimal code generation on ARM64, thus was not implemented.
Architecture |
Register |
Vector |
x64 |
✅ |
✅ |
x86 |
✅ |
✅ |
ARM64 |
✅ |
✅ |
Architecture |
Supported |
Notes |
x64 |
✅ |
|
x86 |
✅ |
|
ARM64 |
✅ |
Will use vector registers when available. |
Architecture |
Supported |
Notes |
x64 |
✅ |
|
x86 |
✅ |
|
ARM64 |
✅ |
2-5 instructions, depending on constant length. |
Architecture |
Supported |
x64 |
✅ |
x86 |
✅ |
ARM64 |
✅ |
Architecture |
to Register |
to Vector |
Notes |
x64 |
✅ |
✅ |
|
x86 |
✅ |
✅ |
|
ARM64 |
✅ |
✅ |
|
Architecture |
Registers |
Vectors |
Notes |
x64 |
✅ |
✅ * |
*Requires scratch register |
x86 |
✅ |
✅ * |
*Requires scratch register |
ARM64 |
✅ * |
✅ * |
*Requires scratch register |
Architecture |
Supported |
Notes |
x64 (register) |
✅ |
Uses scratch register for efficiency. |
x86 (register) |
✅ |
Uses scratch register for efficiency. |
ARM64 (register) |
✅ |
Uses scratch register (required) |
Architecture |
Supported |
Notes |
x64 |
✅ |
+-2GiB |
x86 |
✅ |
+-2GiB |
ARM64 |
✅ |
+-128MiB |
Architecture |
Supported |
Notes |
x64 |
✅ |
|
x86 |
✅ |
|
ARM64 |
✅ |
2 instructions if offset > 0. |
Architecture Specific Operations
Architecture |
Supported |
Notes |
x64 |
✅ |
|
x86 |
❓ |
Unsupported. |
ARM64 (+- 1MiB) |
✅ |
2 instructions. |
ARM64 (+- 4GiB) |
✅ |
3 instructions. |
Architecture |
Supported |
Notes |
x64 |
✅ |
|
x86 |
❓ |
Unsupported. |
ARM64 (+- 1MiB) |
✅ |
2 instructions. |
ARM64 (+- 4GiB) |
✅ |
3 instructions. |
Optimized Push/Pop Operations
Architecture |
Supported |
Notes |
x64* |
✅ |
|
x86* |
✅ |
|
ARM64 |
✅ |
Might fall back to single pop/push if mixing register sizes. |
* Implemented but not used, due to more efficient code generation alternative.
Architecture |
Supported |
Notes |
x64* |
✅ |
|
x86* |
✅ |
|
ARM64 |
✅ |
Might fall back to single pop/push if mixing register sizes. |
* Implemented but not used, due to more efficient code generation alternative.